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1 for more information www.analog.com document feedback typical application features description a 7- bit current dac with pmbus interface the lt c ? 7106 is a precision, pmbus controlled, bidi - rectional current digital-to-analog converter that adjusts the output voltage of any conventional v fb referenced regulator. the lt c7106 can work with the vast majority of power management controllers or regulators to enable digital control of the output voltage. internal power-on reset circuitry keeps the dac output current at zero (high impedance idac) until a valid write takes place. features include a range bit for easy interfacing to almost any impedance resistor divider, and an open-drain gpo output for controlling the run or enable pin of the dc/ dc regulator. for most applications, the current dac error is significantly attenuated with proper design. see more detail about v out accuracy in the applications information section of this data sheet. the lt c7106 is supported by the adi ltpowerplay ? development tool with graphical user interface (gui). applications n 0.8% i dac positive output current accuracy (over?temp) n 1.5% i dac negative output current accuracy (over?temp) n pmbus/i 2 c compliant serial interface n input voltage range : 2.5v to 5.5v n high impedance at idac output when disabled n wide idac operation voltage ( 0.4v to 2.0v ) n 7- bit programmable dac output current for dc/dc v out control n wide range idac output current : 16 a ?to 256 a n programmable slew rate : 500ns ~ 3ms per bit n available in a 10- lead ( 3mm 2mm ) dfn package n general purpose power systems n telecom systems n industrial applications all registered trademarks and trademarks are the property of their respective owners. margin high and margin low pmbus interface ?64a to 0a 0a to 63a 7106 ta01a lt c7106 rev a v out 5v/div 7106 ta01b c1 1f 10k r1 10k r2 r fb1 circuit of figure 11 r fb2 c2 330f l1 r4 10k ltc7106 v dd gnd idac sda v out = 24v scl alert gpo asel0 asel1 v dd 2.5v to 5.5v sda alert scl v dd i dac = ?40a v in dc/dc sw v fb v out run en (0.4v to 2v) v in v ref i dac = 40a 10k r3 i dac = 0a 100ms/div en 2v/div
2 for more information www.analog.com absolute maximum ratings all pins except gnd .................................. C 0.3v to 6.0v operating junction temperature range ... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (note 1) aa a a a a alert a a a order information lead free finish tape and reel part marking* package description temperature range lt c7106 eddb#pbf lt c7106 eddb#trpbf lhcg 10- lead ( 3mm 2mm ) plastic dfn C 40 c to 125 c lt c7106 iddb#pbf lt c7106 iddb#trpbf lhcg 10- lead ( 3mm 2mm ) plastic dfn C 40 c to 125 c consult adi marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to : http : //www.linear.com/leadfree/ for more information on tape and reel specifications, go to : http : //www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http : //www.linear.com/product/ lt c7106 #orderinf o pin configuration lt c7106 rev a
3 for more information www.analog.com electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25 c (note 2), v dd = 3.3v , unless otherwise specified. symbol parameter conditions min typ max units v dd power supply 2.5 ? 5.5 v i q supply quiescent current en high 700 1400 a i shutdown supply quiescent current en = 0v 800 a v uvlo_r undervoltage rising threshold v dd rising 2.35 v v uvlo_f undervoltage falling threshold v dd falling 2.15 v v en_r enable rising threshold v en rising 1.35 v v en_f enable falling threshold v en falling 0.8 v idac_out i dac accuracy full scale positive 0.4 v idac 2v (note 3) range = normal l 62.5 63 63.5 a range = low l 15.5 15.75 16.0 a range = high l 246.7 252.00 255.3 a full scale negative 0.4 v idac 2v (note 3) range = normal ( 0 c to 85 c ) C 64.64 C 64 C 63.36 a range = normal l C 64.96 C 64 C 63.04 a range = low l C 16.36 C 16 C 15.64 a range = high l C 262.50 C 256 C 249.50 a lsb 0.4 v idac 2v range = normal 1 a range = low 0.25 a range = high 4 a inl 0.4 v idac 2v range = normal C 1 1 lsb range = low C 1.5 1.5 lsb range = high C 1.6 1.6 lsb dnl 0.4 v idac 2v range = normal C 0.3 0.3 lsb range = low C 0.5 0.5 lsb range = high C 0.8 0.8 lsb ihz high-z current 0.4 v idac 2v v en = 0 l 20 na digital input : sda, scl v ih 1.4 v v il 0.8 v c pin input capacitance 10 pf open-drain outputs : alertb, gpo, sda v ol output low voltage i sink = 3ma 0.4 v lt c7106 rev a
4 for more information www.analog.com pmb us interface timing characteristics the l denotes the specifications which apply?over the specified operating junction temperature range, otherwise specifications are at t a = 25 c (note 2), v dd = 3.3v , unless otherwise specified. symbol parameter conditions min typ max units f scl serial bus operating frequency 10 400 khz t buf bus free time between stop and start condition 1.3 s t hd_sda hold time after (repeated) start condition 0.6 s t su_sda repeated start condition setup time 0.6 s t su_sto stop condition setup time 0.6 s t hd_dat (out) data hold time 300 900 ns t hd_dat (in) input data hold time 0 ns t su_dat data setup time 100 ns t low clock low period 1.3 10000 s t high clock high period 0.6 s t timeout_smb stuck pmbus timer 30 ms note 1 : stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2 : the lt c7106 is tested under pulsed load conditions such that t j ? ?t a . the lt c7106 e is guaranteed to meet performance specifications from 0 c to 85 c . specifications over the C 40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt c7106 i is guaranteed over the C 40 c to 125 c operating junction temperature range. high junction temperatures degrade operating lifetimes ; operating lifetime is derated for junction temperatures greater than 125 c . note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula : t j = t a + (p d ? ? 55 c /w). note 3 : idac is a bidirectional current dac, controlled by 2 s complementary logic. under the setting of range = normal, i dac ? = ? 63 a for code = 0111111 provides the maximum source current and i dac ? = ? C 64 a for code = 1000000 provides the maximum sink current. max sink current generates the highest v out , while max source current generates the lowest v out . see the operation section for more details. typical performance characteristics quiescent current vs temperature idac leakage current vs temperature pidac full-scale vs temperature t a = 25 c , v dd = 3.3v , v idac = 1.0v , range = normal unless otherwise noted. vid[6:0] = 0111111 lt c7106 rev a 0 1 2 3 idac leakage (na) idac leakage current vs. temp 7106 g02 temperature ( c) ?50 ?10 v en = 0, or v id[6:0] = 0 30 70 110 150 62.500 62.600 62.700 62.800 62.900 63.000 temperature ( c) 63.100 63.200 63.300 63.400 63.500 idac pidac full scale vs. temperature 7106 g03 i range = nominal temp (c) ?50 ?50 ?10 30 70 110 150 500 550 600 650 ?5 700 750 800 850 900 950 1000 i q (a) 7106 g01 40 85 130 ?1
5 for more information www.analog.com typical performance characteristics nidac vs temperature differential nonlinearity integral nonlinearity buck start-up with idac margin high and margin low boost start-up with idac margin high and margin low t a = 25 c , v dd = 3.3v , range = normal unless otherwise noted. vid[6:0] = 1000000 lt c7106 rev a ?64.30 7106 g10 ltc7106 + ltc3784 v out = 24v v in = 12v i dac = 0a 2ms/div gpo 5v/div v out 10v/div ?64.20 7106 g09 i dac = ?40a i dac = 0a i dac = 40a ?64.10 ?64.00 ?63.90 ?63.80 ?63.70 ?63.60 ?63.50 i dac (a) temperature ( c) 7106 g04 code 1 7 13 20 26 32 38 44 ?50 51 57 63 ?0.30 ?0.26 ?0.22 ?0.18 ?0.14 ?0.10 ?0.06 0 ?0.02 0.02 0.06 0.10 dnl (lsb) 7106 g05 code 0 10 20 50 30 40 50 60 70 ?0.15 ?0.12 ?0.09 ?0.06 ?0.03 100 0 0.03 0.06 0.09 0.12 0.15 inl (lsb) integral non?linearity 7106 g06 i dac = ?60a 150 i dac = 60a 10mv/div gpo 5v/div v out 0.3v/div 7106 g07 ltc7106 + ltm4636 v out = 1v i dac = 0a ltc7106 + ltm4636 ?64.50 i dac = ?60a i dac = 60a 100ms/div en 2v/div v out 200mv/div 7106 g08 i dac = 0a v out = 1v ?64.40 ltc7106 + ltc3784 v out = 24v i dac = ?40a i dac = 40a i dac = 0a 100ms/div en 2v/div v out 5v/div
6 for more information www.analog.com pin functions v dd (pin 3) : input supply. bypass this pin to gnd with a capacitor ( 0.1 f to 1 f ). idac (pin 6) : bidirectional current dac output. en (pin 7) : chip enable pin. current dac output is in hi-z state when en is grounded. do not leave en floating. sda (pin 1) : serial bus data input and open-drain output. a pull-up resistor to v dd is required in the application. scl (pin 2) : serial bus clock input. gpo (pin 8) : open-drain digital output. a pull-up resistor to v dd is required. alert (pin 4) : open-drain digital output. a pull-up resistor to v dd is required. ase l1 /ase l0 (pins 10, 9) : serial bus address select inputs. each pin has three states (v dd , floating and gnd) ; these two pins provide 9 addresses. gnd (pin 5) : ground. lt c7106 rev a
7 for more information www.analog.com block diagram + ? en v dd gpo idac sda scl alert asel0 asel1 v ref gnd pmbus interface address adc 7-bit idac vid[6:0] r1 slew rate range 7106 bd lt c7106 rev a
8 for more information www.analog.com operation the lt c7106 is a pmbus controlled 7- bit d/a converter current source. through its pmbus interface, the lt c7106 receives a 7- bit dac code and converts this value to a bidirectional analog output current through the pin idac. by connecting idac to the feedback node of a voltage regulator, i dac can change the output voltage of the regula - tor with the equation : v out = v ref ? (1 + r fb1 /r fb2 ) C i dac ? r fb1 where v ref is the reference voltage of the voltage regula - tor. r fb1 and r fb2 are the resistor divider for the voltage regulator. i dac is the programmed bidirectional current shown in table 2 . a typical application diagram is shown on the front page. therefore, the traditional pure analog designed oriented pwm controller can be controlled by a pmbus interface. this illustrates the flexibility of the lt c7106 providing a pmbus interface to conventional analog dc/dc converters. chip enable (en pin) the lt c7106 is activated by the en pin. it turns on/off the device with threshold of 1.2v . when en is low ( < 1.2v ), idac is in high impedance (hi-z). however, pmbus interface is still active when en is low which means users can program the device and readback the internal register's value. the device will execute the commands of mfr_iout_command , mfr_iout_margin_high , mfr_iout_margin_low after en goes high. slew rate control to prevent abrupt changes in the d/a output current and?subsequently the output voltage of the dc/dc regula - tor, an internal digital programmable slew rate control is included. the slew rate range can be programmed with a 6- bit register from 0.5 s /step to 3.58ms /step with a default value of 3.58ms /step. current range setting and d/a programming the lt c7106 is a 7- bit bidirectional current dac with a 1 a lsb as its default setting. the msb determines the current direction. when msb is 0, i dac is sourcing cur - rent (reducing v out ), which is positive current flowing out of the pin, and when msb is 1, i dac is sinking cur - rent (increasing v out ), which is negative current flowing into the pin. the lt c7106 also provides range high and range low options through its digital interface to change the lsb value to 4 a expanding the output current range and subsequently widening the programmable output voltage range. alternately for higher resolution, the low range is provided with a lsb of 0.25 a . users have ad - ditional flexibility of choosing the resistor divider ratio and resistor values to meet the output specification target. however, the design is most accurate using the nominal range which is the recommended setting. table 1 lists the output current range and table 2 lists the detailed dac codes vs i dac current. table 1. output current range range lsb (a) i min (a) i max (a) nominal 1 C 64 63 range high 4 C 256 252 range low 0.25 C 16 15.75 lt c7106 rev a
9 for more information www.analog.com dac code i dac (a) [ 6 ] [ 5 ] [ 4 ] [ 3 ] [ 2 ] [ 1 ] [ 0 ] nominal range high range low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0.25 0 0 0 0 0 1 0 2 8 0.5 0 0 0 0 0 1 1 3 12 0.75 0 0 0 0 1 0 0 4 16 1 0 0 0 0 1 0 1 5 20 1.25 0 0 0 0 1 1 0 6 24 1.5 0 0 0 0 1 1 1 7 28 1.75 0 0 0 1 0 0 0 8 32 2 0 0 0 1 0 0 1 9 36 2.25 0 0 0 1 0 1 0 10 40 2.5 0 0 0 1 0 1 1 11 44 2.75 0 0 0 1 1 0 0 12 48 3 0 0 0 1 1 0 1 13 52 3.25 0 0 0 1 1 1 0 14 56 3.5 0 0 0 1 1 1 1 15 60 3.75 0 0 1 0 0 0 0 16 64 4 0 0 1 0 0 0 1 17 68 4.25 0 0 1 0 0 1 0 18 72 4.5 0 0 1 0 0 1 1 19 76 4.75 0 0 1 0 1 0 0 20 80 5 0 0 1 0 1 0 1 21 84 5.25 0 0 1 0 1 1 0 22 88 5.5 0 0 1 0 1 1 1 23 92 5.75 0 0 1 1 0 0 0 24 96 6 0 0 1 1 0 0 1 25 100 6.25 0 0 1 1 0 1 0 26 104 6.5 0 0 1 1 0 1 1 27 108 6.75 0 0 1 1 1 0 0 28 112 7 0 0 1 1 1 0 1 29 116 7.25 0 0 1 1 1 1 0 30 120 7.5 0 0 1 1 1 1 1 31 124 7.75 0 1 0 0 0 0 0 32 128 8 0 1 0 0 0 0 1 33 132 8.25 0 1 0 0 0 1 0 34 136 8.5 0 1 0 0 0 1 1 35 140 8.75 0 1 0 0 1 0 0 36 144 9 0 1 0 0 1 0 1 37 148 9.25 dac code i dac (a) [ 6 ] [ 5 ] [ 4 ] [ 3 ] [ 2 ] [ 1 ] [ 0 ] nominal range high range low 0 1 0 0 1 1 0 38 152 9.5 0 1 0 0 1 1 1 39 156 9.75 0 1 0 1 0 0 0 40 160 10 0 1 0 1 0 0 1 41 164 10.25 0 1 0 1 0 1 0 42 168 10.5 0 1 0 1 0 1 1 43 172 10.75 0 1 0 1 1 0 0 44 176 11 0 1 0 1 1 0 1 45 180 11.25 0 1 0 1 1 1 0 46 184 11.5 0 1 0 1 1 1 1 47 188 11.75 0 1 1 0 0 0 0 48 192 12 0 1 1 0 0 0 1 49 196 12.25 0 1 1 0 0 1 0 50 200 12.5 0 1 1 0 0 1 1 51 204 12.75 0 1 1 0 1 0 0 52 208 13 0 1 1 0 1 0 1 53 212 13.25 0 1 1 0 1 1 0 54 216 13.5 0 1 1 0 1 1 1 55 220 13.75 0 1 1 1 0 0 0 56 224 14 0 1 1 1 0 0 1 57 228 14.25 0 1 1 1 0 1 0 58 232 14.5 0 1 1 1 0 1 1 59 236 14.75 0 1 1 1 1 0 0 60 240 15 0 1 1 1 1 0 1 61 244 15.25 0 1 1 1 1 1 0 62 248 15.5 0 1 1 1 1 1 1 63 252 15.75 1 0 0 0 0 0 0 C 64 C 256 C 16 1 0 0 0 0 0 1 C 63 C 252 C 15.75 1 0 0 0 0 1 0 C 62 C 248 C 15.5 1 0 0 0 0 1 1 C 61 C 244 C 15.25 1 0 0 0 1 0 0 C 60 C 240 C 15 1 0 0 0 1 0 1 C 59 C 236 C 14.75 1 0 0 0 1 1 0 C 58 C 232 C 14.5 1 0 0 0 1 1 1 C 57 C 228 C 14.25 1 0 0 1 0 0 0 C 56 C 224 C 14 1 0 0 1 0 0 1 C 55 C 220 C 13.75 1 0 0 1 0 1 0 C 54 C 216 C 13.5 1 0 0 1 0 1 1 C 53 C 212 C 13.25 table 2. idac current and corresponding dac codes operation lt c7106 rev a
10 for more information www.analog.com dac code i dac (a) [ 6 ] [ 5 ] [ 4 ] [ 3 ] [ 2 ] [ 1 ] [ 0 ] nominal range high range low 1 0 0 1 1 0 0 C 52 C 208 C 13 1 0 0 1 1 0 1 C 51 C 204 C 12.75 1 0 0 1 1 1 0 C 50 C 200 C 12.5 1 0 0 1 1 1 1 C 49 C 196 C 12.25 1 0 1 0 0 0 0 C 48 C 192 C 12 1 0 1 0 0 0 1 C 47 C 188 C 11.75 1 0 1 0 0 1 0 C 46 C 184 C 11.5 1 0 1 0 0 1 1 C 45 C 180 C 11.25 1 0 1 0 1 0 0 C 44 C 176 C 11 1 0 1 0 1 0 1 C 43 C 172 C 10.75 1 0 1 0 1 1 0 C 42 C 168 C 10.5 1 0 1 0 1 1 1 C 41 C 164 C 10.25 1 0 1 1 0 0 0 C 40 C 160 C 10 1 0 1 1 0 0 1 C 39 C 156 C 9.75 1 0 1 1 0 1 0 C 38 C 152 C 9.5 1 0 1 1 0 1 1 C 37 C 148 C 9.25 1 0 1 1 1 0 0 C 36 C 144 C 9 1 0 1 1 1 0 1 C 35 C 140 C 8.75 1 0 1 1 1 1 0 C 34 C 136 C 8.5 1 0 1 1 1 1 1 C 33 C 132 C 8.25 1 1 0 0 0 0 0 C 32 C 128 C 8 1 1 0 0 0 0 1 C 31 C 124 C 7.75 1 1 0 0 0 1 0 C 30 C 120 C 7.5 1 1 0 0 0 1 1 C 29 C 116 C 7.25 1 1 0 0 1 0 0 C 28 C 112 C 7 1 1 0 0 1 0 1 C 27 C 108 C 6.75 dac code i dac (a) [ 6 ] [ 5 ] [ 4 ] [ 3 ] [ 2 ] [ 1 ] [ 0 ] nominal range high range low 1 1 0 0 1 1 0 C 26 C 104 C 6.5 1 1 0 0 1 1 1 C 25 C 100 C 6.25 1 1 0 1 0 0 0 C 24 C 96 C 6 1 1 0 1 0 0 1 C 23 C 92 C 5.75 1 1 0 1 0 1 0 C 22 C 88 C 5.5 1 1 0 1 0 1 1 C 21 C 84 C 5.25 1 1 0 1 1 0 0 C 20 C 80 C 5 1 1 0 1 1 0 1 C 19 C 76 C 4.75 1 1 0 1 1 1 0 C 18 C 72 C 4.5 1 1 0 1 1 1 1 C 17 C 68 C 4.25 1 1 1 0 0 0 0 C 16 C 64 C 4 1 1 1 0 0 0 1 C 15 C 60 C 3.75 1 1 1 0 0 1 0 C 14 C 56 C 3.5 1 1 1 0 0 1 1 C 13 C 52 C 3.25 1 1 1 0 1 0 0 C 12 C 48 C 3 1 1 1 0 1 0 1 C 11 C 44 C 2.75 1 1 1 0 1 1 0 C 10 C 40 C 2.5 1 1 1 0 1 1 1 C 9 C 36 C 2.25 1 1 1 1 0 0 0 C 8 C 32 C 2 1 1 1 1 0 0 1 C 7 C 28 C 1.75 1 1 1 1 0 1 0 C 6 C 24 C 1.5 1 1 1 1 0 1 1 C 5 C 20 C 1.25 1 1 1 1 1 0 0 C 4 C 16 C 1 1 1 1 1 1 0 1 C 3 C 12 C 0.75 1 1 1 1 1 1 0 C 2 C 8 C 0.5 1 1 1 1 1 1 1 C 1 C 4 C 0.25 operation table 2. idac current and corresponding dac codes (continued) lt c7106 rev a
11 for more information www.analog.com operation gpo gpo is a general purpose open-drain output pin, which can be set by pmbus command. it is designed to turn on/ off the dc/dc regulator by connecting gpo to the run pin of the regulator. once gpo is set high, it stays high even if the en pin goes low as long as the device is not power cycled. address the pmbus address is selected by ase l0 and ase l1 pins. each pin has three states : high, low and floating. the possible pmbus addresses are shown in table 3 . table 3. address selection ase l1 ase l0 pmbus address gnd gnd 2a gnd v dd 2c gnd float 2e v dd gnd 4a v dd v dd 4c v dd float 4e float gnd 6a float v dd 6c float float 6e pmbus serial interface the lt c7106 serial interface is a pmbus-compliant slave device and can operate at any frequency between 10khz and 400khz . in addition the lt c7106 always responds to the global broadcast address of 0x 5a or 0x 5b ( 7- bit). the serial interface supports the following protocols defined in the pmbus specifications : 1) send command, 2) write byte, 3) group, 4) read byte and 5) read word. the pmbus write operations are not acted upon until a complete valid message is received by the lt c7106 including the stop bit. communication failure attempts to access unsupported commands or writing invalid data to supported commands will result in a cml fault. the cml bit is set in the status_byte command and the alert pin is pulled low. device addressing the lt c7106 offers four different types of addressing over the pmbus interface, specifically : 1) global, 2) device, 3) rail addressing and 4) alert response address (ara). global addressing provides a means of the pmbus master to address all lt c7106 devices on the bus. the lt c7106 global addresses are fixed 0x 5a or 0x 5b (7 bit) or 0x b4 or 0x b6 (8 bit) and cannot be disabled. device addressing provides the standard means of the?pmbus master communicating with a single instance of a lt c7106 . the value of the device address is set by the ase l0 /ase l1 configuration pins. rail addressing provides a means of the pmbus master addressing a set?of?channels connected to the same output rail, simul - taneously. this is similar to global addressing, however, the pmbus? address can be dynamically assigned by using the mfr_rail_address command. it is recom - mended that rail addressing should be limited to command write?operations. all four means of pmbus addressing require the user to employ disciplined planning to avoid addressing conflicts. fault status the status_byte and alert pin provide fault status information of the lt c7106 to the host. bus timeout failure the lt c7106 implements a timeout feature to avoid hang - ing the serial interface. the data packet timer begins at the first start event before the device address write byte. data packet information must be completed within 25ms or the lt c7106 will tri-state the bus and ignore the given data packet. data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), and all data bytes. the user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer be - tween? all? devices sharing the serial bus interface. the lt c7106 supports the full pmbus frequency range from 10khz to 400khz . lt c7106 rev a
12 for more information www.analog.com operation similarity between pmbus, smbus and i 2 c 2- wire interface the pmbus 2- wire interface is an incremental extension of the smbus. smbus is built upon i 2 c with some minor differences in timing, dc parameters and protocol. the pmbus/smbus protocols are more robust than simple i 2 c byte commands because pmbus/smbus provide timeouts to prevent bus hangs and valid operation commands. in general, a master device that can be configured for i 2 c communication can be used for pmbus communication with little or no change to hardware or firmware. repeat start (restart) is not supported by all i 2 c controllers but is required for smbus/pmbus reads. if a general purpose i 2 c controller is used, check that repeat start is supported. for a description of the minor extensions and exceptions pmbus makes to smbus, refer to pmbus specification part 1, revision 1.1 : paragraph 5 : transport. for a description of the differences between smbus and i 2 c, refer to system management bus (smbus) specification version 2.0 : appendix b differences between smbus and i 2 c. pmbus serial interface the lt c7106 communicates with a host (master) using the standard pmbus serial bus interface. the timing diagram, figure 1 , shows the timing relationship of the signals on the bus. the two-bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the lt c7106 is a slave device. the master can com - municate with the lt c7106 using the following formats : ? master transmitter, slave receiver ? master receiver, slave transmitter the following pmbus protocols are supported : ? write byte, send byte ? read byte, read word ? alert response address figure 3 through figure 6 illustrate the aforementioned pmbus protocols. all transactions support gcp (group command protocol). figure 2 is a key to the protocol diagrams in this section. a value shown below a field in the following figures is a mandatory value for that field. the data formats implemented by pmbus are : ? master transmitter transmits to slave receiver. the transfer direction in this case is not changed. ? master reads slave immediately after the first byte. at the moment of the first acknowledgment (provided by the slave receiver) the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter. ? combined format. during a change of direction within a transfer, the master repeats both a start condition and the slave address but with the r/ w bit reversed. in this case, the master receiver terminates the transfer by generating a nack on the last byte of the transfer and a stop condition. examples of these formats are shown in figure 4 and figure 5 . lt c7106 rev a
13 for more information www.analog.com figure 1. timing diagram operation sda scl t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf start condition stop condition repeated start condition start condition t r t f t r t f t high 7106 f01 slave address data byte wr a a p 7106 f02 s 7 s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) x shown under a field indicates that that field is required to have the value of x a acknowledge (this bit position may be 0 for an ack or 1 for a nack) p stop condition pec packet error code master to slave slave to master continuation of protocol 8 1 1 1 x x 1 1 ... slave address command code data byte wr a a a p 7106 f03 s 7 8 8 1 1 1 1 1 1 slave address wr a a p 7106 f04 s 7 8 1 1 1 1 1 command code slave address command code slave address wr a a a p 7106 f05 s 7 8 7 1 data byte low 8 data byte high 8 1 1 1 1 sr 1 1 1 1 1 a 1 rd a slave address command code slave address wr a a sr p 7106 f06 s 7 8 8 1 1 data byte 8 1 1 1 1 1 1 1 1 a rd a figure 2. pmbus packet protocol diagram element key figure 3. write byte protocol figure 4. send byte protocol figure 5. read word protocol figure 6. read byte protocol lt c7106 rev a
14 for more information www.analog.com table 4. lt c7106 supported pmbus commands pmbus code (8 bits) r/w type command name description 0x 01 r/w operation default is on : [ 7 : 0 ] = 0x 80 0x 78 r/w status_byte read fault status : cml, write 1 to reset 0x 98 read pmbus_revision read pmbus revision = 0x 22 for rev 1.2 0x e2 r/w mfr_chip_ctrl [ 7 : 4 ] C reserved : [ 7 : 0 ] = 0x 00 default [ 0 ] = gpo en, [ 1 ] = reserved, [ 2 ] = write protect, [ 3 ] ? = timeout status 0x e4 r/w mfr_dac_ctrl [ 7 : 6 ] = current step control, [ 5 : 0 ] = dac slew rate control 0x e5 r/w mfr_iout_margin_high same format as mfr_iout_command 0x e6 r/w mfr_iout_max clamped value that dac cannot exceed. default 7- bit value of 0x 00 = source current only 0x e7 read mfr_special_id mfr special id for lt c7106 = 0x 8080 0x e8 r/w mfr_iout_command i out margining command (see table 5 ) [ 5 : 0 ] step value, source : [ 6 ] = 0, sink : [ 6 ] = 1 0x ed r/w mfr_iout_margin low same format as mfr_iout_command 0x fa r/w mfr_rail_address set common pmbus address [ 6 : 0 ] , [ 7 ] = 0 enable, [ 7 ] = 1 disable 0x fd write mfr_reset reset pmbus interface to power-on state write data is ignored ; 0, 1, 2 bytes register command details mfr_iout_command the dac output current command is formatted as a 7- bit 2 s complement value. when the operation register?is set to ? 0x 80, dac takes the value stored in this register. setting bit [ 6 ] to 0 sources the current from the ic and bit [ 6 ] to 1 sinks the current into the ic. default value for this register is 0x 00. the valid range of values are from 0x 40 to 0x 3 f. do not attempt to write values outside of this range or undesired behavior may result. writes to this register are inhibited when the wpb, bit [ 2 ] in mfr_chip_ctrl , is set high. mfr_iout_margin_high dac margining register with the same format and rules as mfr_iout_command . the dac value will take the value stored in this register when the operation register is set to margin high, 0x a8 . mfr_iout_margin_low dac margining register with the same format and rules as mfr_iout_command . the dac value will take the value stored in this register when the operation register is set to margin low, 0x 98. mfr_iout_max clamping value that dac cannot exceed. the format is a 7- bit 2 s complement value, the same as the margin registers. therefore, the dac value cannot be a smaller 2 s complement value than what is stored in this register. the 7- bit default value is 0x 00 = cannot sink current. i out cannot be set to a higher value unless this value is changed to a negative number, bit [ 7 ] = 1. setting this register to 0x 40 allows the lt c7106 to sink the maximum current with no clamping. lt c7106 rev a
15 for more information www.analog.com register command details mfr_chip_ctrl this register is for general chip control and status. please refer to table 7 for each bit description. bits description [ 7 : 4 ] reserved [ 3 ] timeout status : 0 = no pmbus timeout occurred 1 = a timeout occurred writing a 1 to this bit will clear this bit [ 2 ] write protect for margin registers 0 = write allowed 1 = writes inhibited [ 1 ] reserved [ 0 ] gpo, general purpose output 0 = gpo pulls open drain to gnd 1 = hi-z on gpo mfr_dac_ctrl 8- bit register to control the i dac lsb current value and the timer count for the slew rate control. default value = 0x 40. bits description [ 7 : 6 ] selector range for i dac step current : b 00 = 0.25 a /step, range low b 01 = 1.0 a /step, nominal b 10 = 4.0 a /step, range high b 11 = reserved [ 5 : 0 ] selector for time in s/step default value 0x 00 = max = 3584 s /step see table 6 for allowable values only a power cycle, por, will reset this register to prevent unwanted immediate current changes in idac. mfr_reset will not reset this register. in addition, idac must be at 0x 00 to change the current range selector to prevent unwanted large swings in i dac current. the time step selector, bits [ 5 : 0 ] , can be changed at any time. table 5. programmable delay per current step slew rate timer clock (s/step) [ 5 : 0 ] [ 5 : 0 ] [ 5 : 0 ] 0 0 0 0 0 0 = 3584 0 1 0 0 0 0 = 16 1 0 0 0 0 0 = 256 0 0 0 0 0 1 = 0.5 0 1 0 0 0 1 = 20 1 0 0 0 0 1 = 320 0 0 0 0 1 0 = 1.0 0 1 0 0 1 0 = 24 1 0 0 0 1 0 = 384 0 0 0 0 1 1 = 1.5 0 1 0 0 1 1 = 28 1 0 0 0 1 1 = 448 0 0 0 1 0 0 = 2.0 0 1 0 1 0 0 = 32 1 0 0 1 0 0 = 512 0 0 0 1 0 1 = 2.5 0 1 0 1 0 1 = 40 1 0 0 1 0 1 = 640 0 0 0 1 1 0 = 3.0 0 1 0 1 1 0 = 48 1 0 0 1 1 0 = 768 0 0 0 1 1 1 = 3.5 0 1 0 1 1 1 = 56 1 0 0 1 1 1 = 896 0 0 1 0 0 0 = 4.0 0 1 1 0 0 0 = 64 1 0 1 0 0 0 = 1280* 0 0 1 0 0 1 = 5.0 0 1 1 0 0 1 = 80 1 0 1 0 0 1 = 1280 0 0 1 0 1 0 = 6.0 0 1 1 0 1 0 = 96 1 0 1 0 1 0 = 1536 0 0 1 0 1 1 = 7.0 0 1 1 0 1 1 = 112 1 0 1 0 1 1 = 1792 0 0 1 1 0 0 = 8.0 0 1 1 1 0 0 = 128 1 0 1 1 0 0 = 2560* 0 0 1 1 0 1 = 10 0 1 1 1 0 1 = 160 1 0 1 1 0 1 = 2560 0 0 1 1 1 0 = 12 0 1 1 1 1 0 = 192 1 0 1 1 1 0 = 3584* 0 0 1 1 1 1 = 14 0 1 1 1 1 1 = 224 1 0 1 1 1 1 = 3584 * duplicate encoding lt c7106 rev a
16 for more information www.analog.com figure 7. mfr_rail_address data byte pmbus command details 7106 f07 b7 b0 7-bit address disable clear b7 to enable rail address mfr_reset this command provides a means by which the user can perform a reset of the lt c7106 . all latched faults ( alert and status register) and register contents will be reset to a power-on condition by this command. v out will remain in regulation but may change due to the reset of the margin registers. this write-only command accepts zero, one, or two data bytes but ignores them. mfr_rail_address the mfr_rail_address command allows all devices to share a common address, such as all devices attached to a single power supply rail. the desired 7- bit address value is written to the 7 bits of the data byte. the msb (bit b7 ) must be set low to enable communication using the mfr_rail_address address. setting this bit disables this address. the default for this register is 0x 80. operation the operation command is used to turn the unit on/off and for margining the output voltage. the on bit is automatically reset to on after a master shutdown (en), power cycle, or mfr_reset command. the margin_low /high bits command the i out refer - ence to the offset value stored in either the mfr_iout_ margin_high or mfr_iout_margin_low . this command has one data byte. it will accept one or two but ignores the second byte. table 6. supported operation command register values action value turn off immediately 0x 00 turn on 0x 80 margin low 0x 98 margin high 0x a8 pmbus_revision the pmbus_revision command indicates the revision of the pmbus to which the device is compliant. the lt c7106 is pmbus version 1.2 compliant in both part i and part ii. this read-only command has one data byte and will return? 0x 22. mfr_special_id the 16- bit word representing a unique identification for ltpowerplay. this read-only command has 2 data bytes and is set to 0x 8080. the user should only perform command writes to this address. if a read is performed from this address and the rail devices do not respond with exactly the same value, the lt c7106 will detect bus contention and abort its read command with no cml or alertb set. this command accepts one or two data bytes but the second is ignored. lt c7106 rev a
17 for more information www.analog.com status_byte the status_byte command returns one byte of informa - tion with a summary of the unit s fault condition. see table 7 for a list of the status bits that are supported and the conditions in which each bit is set. certain bits when set in the status_byte also cause the alert pin to be asserted. writing a 1 to a particular bit in the status byte will attempt to reset that fault in the status byte and the alert pin. if pmbus command details the fault is still present the status byte bit and alert will remain asserted. if the alert has previously been cleared by an ara message, the alert will be re-asserted. if the fault is no longer present, the alert pin will be de-asserted and the fault bit in the status byte will be cleared. all bits in the status byte are also cleared by toggling the run_mstr pin or the on bit in operation. the bit will immediately be set again if the fault remains. table 7. status byte bit descriptions and conditions bit description condition set alert ? clearable by writing 1 to bit ? 0 (lsb) none of the above mfr_vout_max register exceeded no yes 1 communication failure (see note 1) yes yes 2 temperature fault not implemented 3 v in undervoltage fault not implemented 4 output overcurrent fault not implemented 5 output overvoltage fault not implemented 6 off not implemented 7 busy not implemented note 1 : communication failure is one of following faults : host sends too few bits, host reads too few bits, host writes too few bytes, improper r/w bit set, unsupported command code, attempt to write to a read-only command. see pmbus specification v1.2, part ii, sections 10.8 and 10.9 for more information. lt c7106 rev a
18 for more information www.analog.com i dac accuracy the lt c7106 provides three ranges of i dac output current. however, only nominal range (lsb = 1 a ) is optimized with the highest accuracy. it is recommended that users design the resistor divider using the nominal range of the idac setting. two s complementary code vid [ 6 : 0 ] of the lt c7106 is in the format of two s comple - mentary. from table 2 , it is easy to program the register once the desired output current is known. for example, if output current is 20 a , then set vid [ 6 : 0 ] ? = 0010100. if the output current is C 20 a , then set vid [ 6 : 0 ] ? = ?1101100 for the nominal i dac setting. v out accuracy when i dac = 0, define : v o u t 0 = v r e f 1 + r f b 1 r f b 2 ? ? ? ? ? ? (1) referring to figure 8 , the output voltage is set according to : v o u t = v r e f 1 + r f b 1 r f b 2 ? ? ? ? ? ? ? i d a c ? r f b 1 (2) applications information define ? v out as the v out error caused by the i dac error ? i dac , then we can derive the following equation from equation (1) and (2) : ? v o u t v o u t = ? i d a c / i d a c r a t i o ? 1 ? ? ? ? ? ? (3) where : r a t i o = v o u t 0 i d a c ? r f b 1 (4) it is clear that when ratio < 0 or ratio 2, the v out error can be attenuated from the i dac error : | ? v o u t v o u t | | ? i d a c i d a c | (5) in the case of margin high, i dac < 0 so ratio < 0. therefore, the v out error is always smaller than the i dac error by a factor of : v o u t 0 i d a c ? r f b 1 C 1 (6) in the case of margin low, i dac > 0. so the v out error will only be attenuated when : r a t i o = v o u t 0 i d a c ? r f b 1 > 2 o r i d a c ? r f b 1 < v o u t 0 2 (7) in other words, as long as v out is margining low within 50% of the v out default value, v out0 , the v out error won't be larger than the i dac error. design examples the lt c7106 can work with almost all the power manage - ment controllers or regulators. figure 9 , figure 10 and figure 11 show three design examples using the lt c7106 to control the output voltage with a monolithic buck regu - lator, an module ? and a boost controller. 7106 f08 figure 8. setting the output voltage using the lt c7106 lt c7106 rev a r fb1 r fb2 v out i dac v ref ltc7106
19 for more information www.analog.com case one assume that the lt c7150 s, a monolithic buck regula - tor, provides a 1.5v output and requires to margin low v out from 1.5v to 1.0v (see figure 9 ). the v fb is 0.6v and the voltage dividers are external. in order to achieve the best accuracy of the lt c7106 , it is recommended to design i dac in nominal range. also within certain current range (nominal, high or low), the larger the absolute i dac current amplitude is, the better accuracy the lt c7106 can achieve. so it is easy to choose r top ? = ? 10k ? and r bot ? = ? 6.65k ? . then i dac = ( 1.5v C 1.0v )/ 10k ? = + 50 a . choose mfr_control [ 6 : 5 ] = 00 (range = nominal) to set i dac lsb = 1 a . by looking in table 2 , choose dac [ 6 : 0 ] = 0110010 to set the i dac = + 50 a , which will margin v out from 1.5v to 1.0v . figure 9. using the lt c7106 to margin low monolithic buck regulator lt c7150 s providing 1.5v to 1.0v at 20a applications information + 7106 f09 pmbus interface lt c7106 rev a 22pf 4.7f ltc7106 v dd gnd sda scl alert gpo asel0 gpo asel1 v dd 2.5v to 5.5v sda alert scl +50a en ltc7150s pgood v out intv cc run track/ss ith sw fb v out ? mode/sync sgnd rt 1f 1.5v/20a 6.65k 10k 100f 2 to margin low v out from 1.5v to 1v pvin svin phmode clkout 10k 10k 10k 162k 1nf v in 3.1v to 20v 22f 2 idac 10k 10k 10k 330f 0.25h
20 for more information www.analog.com applications information figure 10. using the lt c7106 to margin high module lt m4636 providing 1.2v to 2.0v at 40a case two in this case, the module lt m4636 provides a 1.2v output and requires to margin high v out from 1.2v to 2.0v (see figure 10 ). the v fb of the lt m4636 is again? 0.6v . however, the top voltage divider is internal (r top = 4.99k ? ), so the r bot is also fixed at 4.99k ? . then i dac ? = ?( 1.2v ? C ? 2.0v )/ 4.99k ? ? = ? C 160 a . so we have to choose mfr_control [ 6 : 5 ] = 10 (range? = ?high) to set i dac lsb = 4 a . from table 3 , choose dac [ 6 : 0 ] = 1011000 to set the i dac ? = C 160 a , which will margin v out from 1.2v to 2.0v . 7106 f10 pmbus interface lt c7106 rev a 22f 0.1f 34.8k 4.7f 470f 4.99k 100f ltc7106 v dd gnd gpo sda scl alert gpo asel0 asel1 v dd 2.5v to 5.5v sda alert 1f scl en ltm4636 runc runp hizreg freq mode/pllin snsp1 pv cc 10k track/ss v out v outs1 + v outs1 - v fb snsp2 compa compb v in intv cc 10k pv cc 25v 4.70v to 15v 16v 5 pv cc intv cc intv cc 3 sgnd 10k pgnd temp + temp ? optional temp monitor pins not used in this circuit: clkout,gmon, pgood,phmode,pwm, sw,test1,test2,test3,test4,tmon 6.3v x4 v out 22pf 1.2v, 40a v in < = 5.5v, tie v in , intv cc and pv cc together, tie runp to gnd, v in > 5.5v, then operate as shown idac 160a to margin high v out from 1.2v to 2v 10k 115k 100f
21 for more information www.analog.com figure 11. using the lt c7106 with a boost controller to vary v out from 28v to 18v applications information case three the lt c7106 can also work with boost converters. in this case, the lt c3784 , a synchronous boost controller, provides a 2- phase 28v / 10a output and requires to control v out from 28v to 18v (see figure 11 ). the vfb is 1.2v and the voltage dividers are external. based on the same design criteria in case one, we can choose r top = 200k and r bot = 8.97k for the best accuracy. then i dac = ( 28v C 18v )/ 200k = + 50 a . choose mfr_control [ 6 : 5 ] = 00 (range nominal) to set i dac lsb = 1 a . by looking in table 2 , choose dac [ 6 : 0 ] = 0001110 to set the i dac = + 50a , which will margin v out from 28v to 18v . v batt 12v down to 2.3v after start-up if v bias is powered from v out 7106 f11 pmbus interface lt c7106 rev a v dd gnd sda scl alert gpo asel0 asel1 v dd 2.5v to 5.5v 0.1 f sda alert scl en ltc3784 pgood freq ovmode v bias mode/pllin gpo ith sense1 ? sense1 + tg1 sw1 intv cc sgnd ss pgnd +50a to margin low v out from 28v to 18v intv cc 100pf 15nf 8.66k 0.1f 100k 47f bg1 boost1 sense2 ? sense2 + 1f sw2 bg2 boost2 tg2 vfb 4.7f 4m 0.1 f 200k 3.3h 10k 4m 3.3h v out 28v at 10a 220f 8.97k idac 10k 10k 10k ltc7106
22 for more information www.analog.com package description please refer to http : //www.linear.com/product/ lt c7106 #packaging for the most recent package drawings. 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.64 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.39 0.05 (2 sides) 3.00 0.10 (2 sides) 1 5 10 6 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb10) dfn 0905 rev ? 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.39 0.05 (2 sides) recommended solder pad pitch and dimensions 0.64 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc ddb package 10-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1722 rev ?) lt c7106 rev a
23 for more information www.analog.com revision history rev date description page number a 04/18 clarified mfg_rail_address and mfg_special_id paragraphs changed from status word to status byte 15 16 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. lt c7106 rev a
24 for more information www.analog.com d16851-0-4/18(a) www.analog.com ? analog devices, inc. 2017-2018 related parts typical application figure 12. margining a lt8640 s from 1.8v to 1.5v at 6a 7106 f12 pmbus interface 1f external source >3.1v or gnd lt8640s sw v in en/uv bias rt fb gnd 10pf 100f 1210 x5r/x7r 6.04k v out 1.8v 6a 4.7f v in 3.4v to 22v (42v transient) 17.8k 1h 6.98k f sw = 2mhz l: xel6030 part number description comments lt c3605 / lt c3605 a 20v , 5a synchronous step-down regulator 4v < v in < 20v , 0.6v < v out < 20v , 96% maximum efficiency, 4mm ? 4mm qfn-24 package lt c3626 20v , 2.5a synchronous step-down regulator with current and temperature monitoring 95% efficiency, v in : 3.6v to 20v , v out(min) = 0.6v , i q = 300 a , isd? < 15 a , 3mm ? 4mm qfn-20 lt c3636 20v , dual 6a synchronous step-down regulator 95% efficiency, v in : 3.1v to 17v , v out(min) = 0.6v , i q < 8a (both channels enabled), isd < 1a , 3mm ? 5mm qfn-24 package lt c3779 150v v in and v out synchronous 4- switch buck-boost dc/dc controller 4.5v v in 150v , input or output average current loop, pll, tssop-38 package lt c3784 low i q , multiphase, dual channel single output synchronous step-up dc/dc controller 4.5v (down to 2.5v after start-up) v in 60v , v out up to 60v , pll fixed frequency 50khz to 900khz , i q = 28a lt c3807 38v , low i q , synchronous step-down controller with 24v ?output voltage capability pll fixed frequency 50khz to 900khz , 4v v in 38v , 0.8v ? ?v out ? ? 24v , i q = 50 a lt c3871 100v bidirectional polyphase ? buck or boost controller dynamic regulation of v in , v out and current, pll, current monitor, 48- lead lqpf package lt m ? 4636 40a dc/dc module step-down regulator complete 40a switch mode power supply, 4.75v v in 15v , 0.6v v out 3.3v , 16mm ? 16mm ? 7.12mm bga lt c7150 s 20v , 20a synchronous step-down regulator 93% efficiency, v in : 3.1v to 20v , v out(min) = 0.6v , output remote sense, 42- lead 6mm ? 5mm ? 1.3mm bga package lt ? 8640s 42v , 6a synchronous step-down silent switcher ? 2 i q = 2.5 a , v in(min) = 3.4v , v out(max) = 42v , v out(min) = 0 lt c7106 rev a sda scl alert gpo asel0 asel1 v dd 2.5v to 5.5v sda alert gpo scl 0a to 50a en idac 10k 1f 10k 10k 10k ltc7106 v dd gnd

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